IP/SOC/ASIC VERIFICATION ENGINEER/SR. ENGINEER/LEAD

Dear Job Aspirants:

Rush your resume for a bright career opportunity with leading world-class technology & product-based MNC.

The company has a culture of innovation that began with the invention of the Field Programmable Gate Array (FPGA).

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, you have the right place here. You have deep care about creating meaningful development experiences while building a strong sense of belonging and connection. The company fosters an environment of empowered learning, wellness, community engagement, and recognition.

JOB DESCRIPTION

• Masters/ Bachelors in EE/EC/CS with 4-10 years of experience in IP/SoC/ASIC Verification.
• Experience with System Verilog and UVM. Develop verification IP which can be reused at different levels of verification: block level, sub-system level, SoC level, etc.
• Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage and assertions, preferably using System Verilog.
• Knowledge in a networking domain like Ethernet, Cryptography protocol – an advantage.
• Expertise in Scripting languages like Perl/Python.
• Excellent communication, problem-solving and analytical skills.

Position – Engineer/Sr. Engineer/Lead

Salary – Best in the Industry with Benefits and RSUs

Qualification – BE/B.TECH/ME/M.TECH from recognised University