RTL Design Engineer

Position Overview

Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications.

Key Responsibilities

• Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect.
• Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs.
• Configure CMN topologies using Arm Socrates for optimized performance and scalability.
• Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
• Optimize designs for bandwidth, latency, and power in AI/HPC workloads.
• Support synthesis, timing closure, and FPGA prototyping and Design Verification team
• Document microarchitecture and design specifications.

Required Qualifications

• Education: BS/MS/PhD in Electronics/Computer Engineering.
• Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3).
• Skills:
  • Expert in Verilog/SystemVerilog RTL design.
  • Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects.
  • Deep understanding in system architecture, coherence and cache
  • Experience with Arm Socrates for CMN configuration.
  • Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols.
  • Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler).
• Experience with AI/HPC or datacenter SoC design.
• Knowledge of DDR5, HBM3, or chiplet-based architectures.
• Familiarity with UALink or Ultra Ethernet.
• Strong problem-solving and collaboration skills.