SYSTEM VERILOG VERIFICATION ENGINEER

Dear Job Aspirants:

Rush your resume for a bright career opportunity with leading world-class technology & product-based MNC.

The company has a culture of innovation that began with the invention of the Field Programmable Gate Array (FPGA).

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, you have the right place here. You have deep care about creating meaningful development experiences while building a strong sense of belonging and connection. The company fosters an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – that improves the way we live and work.

JOB DESCRIPTION

Bachelor’s Degree with 5-9 years

• Strong experience with development of UVM, OVM, VMM, Verilog, System Verilog test benches for full chip test bench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
• Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus.
• Verification experience in full chip verification is a plus.
• Familiarity with verification management tools as well as understanding ofdatabase management particularly as it pertains to regression management is aplus.
• Verification experience in PCIe, Processors, Graphics is a plus.
• Experience with formal property checking tools such as Cadence, Synopsys.
• Experience with GLS, power verification, reset verification,checking, abstraction.

Position – Engineer/Sr. Engineer/Lead

Salary – Best in the Industry with Benefits and RSUs

Qualification – BE/B.TECH/ME/M.TECH from recognised University